Arbitration

Whenever the bus is free, any unit may start to transmit a message. If 2 or more units start transmitting messages at the same time, the bus access conflict is resolved by bitwise arbitration using the IDENTIFIER. The mechanism of arbitration guarantees that neither information nor time is lost. If a DATA FRAME and a REMOTE FRAME with the same IDENTIFIER are initiated at the same time, the DATA FRAME prevails over the REMOTE FRAME. During arbitration every transmitter compares the level of the bit transmitted with the level that is monitored on the bus. If these levels are equal the unit may continue to send. When a ’recessive’ level is sent and a ’dominant’ level is monitored (see Bus Values), the unit has lost arbitration and must withdraw without sending one more bit.

Sleep Mode / Wake-up

To reduce the system’s power consumption, a CAN-device may be set into sleep mode with-out any internal activity and with disconnected bus drivers. The sleep mode is finished with a wake-up by any bus activity or by internal conditions of the system. On wake-up, the internal activity is restarted, although the transfer layer will be waiting for the system’s oscillator to stabilize and it will then wait until it has synchronized itself to the bus activity (by checking for eleven consecutive ’recessive’ bits), before the bus drivers are set to “onbus” again. In order to wake up other nodes of the system, which are in sleep-mode, a special wake-up message with the dedicated, lowest possible IDENTIFIER (rrr rrrd rrrr; r = ’recessive’, d = ’dominant’) may be used.

Ethernet Controller Features:

• IEEE 802.3 compatible Ethernet controller

• Integrated MAC and 10BASE-T PHY

• Supports one 10BASE-T port with automatic polarity detection and correction

• Supports Full and Half-Duplex modes

• Programmable automatic retransmit on collision

• Programmable padding and CRC generation

• Programmable automatic rejection of erroneous packets

• SPI Interface with clock speeds up to 20 MHz

Buffer:

• 8-Kbyte transmit/receive packet dual port SRAM

• Configurable transmit/receive buffer size

• Hardware-managed circular receive FIFO

• Byte-wide random and sequential access with auto-increment

• Internal DMA for fast data movement

• Hardware assisted checksum calculation for various network protocols

Medium Access Controller (MAC) Features:

• Supports Unicast, Multicast and Broadcast packets

• Programmable receive packet filtering and wake-up host on logical AND or OR of the following:

- Unicast destination address

- Multicast address

- Broadcast address

- Magic Packet™

- Group destination addresses as defined by 64-bit hash table

- Programmable pattern matching of up to 64 bytes at user-defined offset

Physical Layer (PHY) Features:

• Loop back mode

• Two programmable LED outputs for LINK, TX,

RX, collision and full/half-duplex status

Operational:

• Six interrupt sources and one interrupt output pin

• 25 MHz clock input requirement

• Clock out pin with programmable prescaler

• Operating voltage of 3.1V to 3.6V (3.3V typical)

• 5V tolerant inputs

• Temperature range: -40°C to +85°C Industrial, 0°C to +70°C Commercial (SSOP only)

• 28-pin SPDIP, SSOP, SOIC, QFN packages